The present invention relates to an erase operation in a non-volatile memory device. More particularly, the present invention relates to a method of performing an erase operation in a non-volatile memory device for enhancing threshold voltage distribution characteristic after an erase operation is performed in a memory device having multi level cell MLC.
Recently, multi bit cells for storing a plurality of data in one memory cell has been actively studied so as to enhance the degree of integration of a flash memory. This memory cell is referred to as a multi level cell MLC. A memory cell for storing one data bit is referred to as a single level cell SLC.
The MLC has a plurality of threshold voltage distributions so as to store a plurality of data. This means that data are differently stored depending on the threshold voltage distributions.
Hereinafter, an erase operation in accordance with the threshold voltage distributions will be described in detail.
Firstly, a pre-program process is performed so as to shift the threshold voltage distributions into the threshold voltage distribution having highest level.
FIG. 1A is a view illustrating a process of applying a voltage in a pre-program for erase of a non-volatile memory device.
In FIG. 1A, to perform the pre-program, a program voltage Vpgm is applied to word lines WL of every cell, a power supply voltage VDD is provided to a drain select line DSL related to a drain select transistor DST, and a voltage of 0V is applied to a source select line SSL related to a source select transistor SST. In addition, a program operation is performed in a unit of a block by applying the power supply voltage VDD to a common ground line after providing a voltage of 0V to a substrate. Here, one block has a plurality of word lines WL, and a non-volatile memory device includes generally a memory cell array (not shown) having blocks.
FIG. 1A illustrates only a part of cell strings so as to show a process of applying a voltage in the pre-program.
In case that the program operation is performed by applying the voltages as described above, threshold voltage distributions of every memory cell are shifted into the threshold voltage distribution having highest level.
Subsequently, an erase operation is performed on the memory cells after the threshold voltage distributions are shifted into the threshold voltage distribution having highest level.
FIG. 1B is a view illustrating a process of applying a voltage for erase of the non-volatile memory device.
In FIG. 1B, to perform the erase operation, the DSL and the SSL are converted into a floating state, and a voltage of 0V is applied to every word line WL. Then, a high voltage of 20V is applied to the substrate. As a result, data of every cell in a corresponding block are erased, and threshold voltage of a corresponding memory cell is downed to a voltage of below 0V. Here, in case that the memory cell is over-erased in accordance with its characteristics, a problem exists in that the threshold voltage of the memory cell is downed to a voltage smaller than desired threshold voltage.
To compensate above problem, a soft program is performed.
FIG. 1C is a view illustrating a process of applying a voltage in the soft program for erase of the non-volatile memory device.
In FIG. 1C, to perform the soft program, a voltage of 0V is applied to the substrate, and the power supply voltage VDD and a voltage of 0V are provided to the DSL and the SSL, respectively. Then, a program operation is performed by applying the program voltage Vpgm to every word line WL so that the over-downed threshold voltage is changed to a voltage of below 0V but is not too low, i.e. the memory cell has the threshold voltage distribution having desired narrow width. Here, the program voltage Vpgm is set so that the memory cells are not programmed to a voltage of above 0V.
Hereinafter, a verifying operation performed after the soft program is finished will be described with reference to accompanying drawing FIG. 1C.
FIG. 1D is a view illustrating a process of applying a voltage for the verifying operation after the soft program in FIG. 1C.
In FIG. 1D, the verifying operation is performed column by column in a unit of a block. Particularly, a read operation is performed by applying the power supply voltage VDD to the DSL and SSL in each of the columns, and applying a voltage of 0V to every word line WL. Here, it is discriminated through the read operation whether or not the soft program is normally performed. On the other hand, in case that at least one memory cell is passed on the verifying voltage, it is discriminated that whole columns related to the memory cell are passed.
In case that the erase operation is performed on the MLC through a method described above, a threshold voltage distribution is not narrowed when the erase operation is finished because the verifying operation is performed in a unit of a column after erasing the memory cell in a unit of a block. As a result, a memory cell having the threshold voltage distribution affects to its surrounding memory cell through interference effect when the program operation on the surrounding memory cell is performed. Accordingly, the threshold voltage distribution becomes wholly wide.
To solve this problem, the verifying operation may be performed bit by bit. However, in this case, a time required for the verifying operation is incrcased, and so efficiency of the erase operation may be lowered.